Impact of Scaling Gate Insulator Thickness on the Performance of Carbon Nanotube Field Effect Transistors (CNTFETs)

As scaling down Si MOSFET devices degrade device performance in terms of short channel effects. Carbon nanotube field effect transistor (CNTFET) is one of the novel nanoelectronics devices that overcome those MOSFET limitations. The carbon nanotube field effect transistors (CNTFETs) have been explored and proposed to be the promising candidate for the next generation of integrated circuit (IC) devices. To explore the role of CNTFETs in future integrated circuits, it is important to evaluate their performance. However, to do that we need a model that can accurately describe the behavior of the CNTFETs so that the design and evaluation of circuits using these devices can be made. In this paper, we have investigated the effect of scaling gate insulator thickness on the device performance of cylindrical shaped ballistic CNTFET in terms of transfer characteristics, output characteristics, average velocity, gm/Id ratio, mobile charge, quantum capacitance/insulator capacitance, drive current (Ion), Ion / Ioff ratio, transconductance, and output conductance. We concluded that the device metrics such as Ion, Ion / Ioff ratio, transconductance, and output conductance increases with the decrease in gate insulator thickness. Also, we concluded that the gate insulator thickness reduction causes subthreshold slope close to the theoretical limit of 60 mV/decade and DIBL close to zero at room temperature. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/3100

Performance of a Double Gate Nanoscale MOSFET (DG-MOSFET) Based on Novel Channel Materials

In this paper, we have studied a double gate nanoscale MOSFET for various channel materials using simulation approach. The device metrics considered at the nanometer scale are subthreshold swing (SS), drain induced barrier lowering (DIBL), on and off current, carrier injection velocity (vinj), etc. The channel materials studied are Silicon (Si), Germanium (Ge), Gallium Arsenide (GaAs), Zinc Oxide (ZnO), Zinc Sulfide (ZnS), Indium Arsenide (InAs), Indium Phosphide (InP) and Indium Antimonide (InSb). The results suggest that InSb and InAs materials have highest Ion and lowest Ioff values when used in the channel of the proposed MOSFET. Besides, InSb has the highest values for Ion / Ioff ratio, vinj, transconductance (gm) and improved short channel effects (SS = 59.71 and DIBL = 1.14, both are very close to ideal values). More results such as effect of quantum capacitance verses gate voltage (Vgs), drain current (Ids) vs. gate voltage and drain voltage (Vds), ratio of transconductance (gm) and drain current (Id) vs. gate voltage, average velocity vs. gate voltage and injection velocity (Vinj) for the mentioned channel materials have been investigated. Various results obtained indicate that InSb and InAs as channel material appear to be suitable for high performance logic and even low operating power requirements for future nanoscale devices as suggested by latest ITRS reports. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/3097

Effect of Gate Length Scaling on Various Performance Parameters in DG-FinFETs: a Simulation Study

This paper presents a simulation study on the gate length scaling of a double gate (DG) FinFET. To achieve channel lengths smaller than 20 nm, innovative device architectures will be necessary to continue the benefits previously acquired through scaling. In order to obtain desirable control of short channel effects (SCEs), the thickness or the horizontal width of a fin in a FinFET should be less than two-third of its gate length and the semiconductor fin should be thin enough in the channel region to ensure forming fully depleted device. The effect of decreasing gate length (Lg) is to deplete more of the region under the inversion layer, which can be easily visualized if the source and drain are imagined to approach one another. If the channel length L is made too small relative to the depletion regions around the source and drain, the SCEs associated with charge sharing and punch through can become intolerable. Thus, to make L small, the depletion region widths should be made small. This can be done by increasing the substrate doping concentration and decreasing the reverse bias. Drain induced barrier lowering (DIBL) increases as gate length is reduced, even at zero applied drain bias, because the source and drain form pn junction with the body, and have associated built-in depletion layers associated with them that become significant partners in charge balance at short channel lengths, even with no reverse bias applied to increase depletion width. The subthreshold slope increases as the device becomes shorter. In fact, when the device becomes very short, the gate no longer controls the drain current and the device cannot be turned off. This is caused by punch through effect. The subthreshold swing (SS) changes with the drain voltage. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/2960

Effect of drift region doping and coulmn thickness variations in a super junction power MOSFET: a 2-D simulation study

In this paper, a power SJMOSFET (Super junction MOSFET) transistor is simulated using PISCES-II, a 2-D numerical device simulator. The doping densities and device dimensions are chosen so as to simulate a typical device structure. These simulations are aimed at understanding the device physics through various electrical quantities like potential distribution, electric field distribution, and electron concentrations etc. in different regions of the device both in on/off states. The effects of doping variations in the ‘n’ and ‘p’ pillars of the SJMOSFET along with the variations in the column thickness of the device were investigated. Various results obtained reveal that device having equal doping in the n and p pillars and having equal width of these pillars gives the best results. The current density is maximum and the charge imbalance is minimum for this case, however the breakdown voltage increases when the width of the n pillar is decreased. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/2793

FLASH MEMORY DEVICES WITH METAL FLOATING GATE/METAL NANOCRYSTALS AS THE CHARGE STORAGE LAYER: A STATUS REVIEW

Traditional flash memory devices consist of Polysilicon Control Gate (CG) – Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) – Polysilicon Floating Gate (FG) – Silicon Oxide (Tunnel dielectric) – Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect.  Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer

TRIBOELECTRIC NANOGENERATORS (TENG): FACTORS AFFECTING ITS EFFICIENCY AND APPLICATIONS

The demand for energy is increasing tremendously with modernization of the technology and requires new sources of renewable energy. The triboelectric nanogenerators (TENG) are capable of harvesting ambient energy and converting it into electricity with the process of triboelectrification and electrostatic-induction. TENG can convert mechanical energy available in the form of vibrations, rotation, wind and human motions etc., into electrical energy there by developing a great scope for scavenging large scale energy. In this review paper, we have discussed various modes of operation of TENG along with the various factors contributing towards its efficiency and applications in wearable electronics

A CRITICAL REVIEW ON THE MATERIAL ASPECTS OF TRIBOELECTRIC NANOGENERATORS (TENG)

Triboelectric nanogenerators (TENG) take the advantage of coupling effect for harvesting energy in the area of electronics for various self-powered applications. These nanogenerators are capable of converting energy in our surroundings into electrical energy by using the process of electrostatic induction and contact electrification. Triboelectric layers of a TENG are formed basically with the use of various polymers, metals and other inorganic materials like PTFE (Poly tetra fluoro ethylene), PDMS (polydimethyl siloxane), FEP (Fluorinated ethylene propylene) and Kapton. Selection of different materials for the device fabrication is very important since it contribute towards the triboelectric effect and also forms the fundamental structure for the proposed TENG device. In this review article, we emphasis mainly on various triboelectric materials considering factors such as stability, flexibility, power density etc., to improve upon the electrical output of the devices for different applications

Impact of SWCNT Band Gaps on the Performance of a Ballistic Carbon Nanotube Field Effect Transistors (CNTFETs)

Band gap is an important property in designing single-walled carbon nanotube (SWCNT) for nanoelectronic devices. This paper describes the impact of SWCNT band gaps on the performance of a ballistic carbon nanotube field effect transistor (CNTFET) using the 2D numerical simulator. The results demonstrate that with the reduction in SWCNT band gap the performance parameters such as transconductance, output conductance, Ion/Ioff current ratio, gain, and carrier injection velocity enhanced while the short channel effects subthreshold slope and drain-induced barrier lowering get suppressed. The enhanced device performance and reduced short channel effects of CNTFET with the reduction in SWCNT band gaps signifying that the CNTFET is a suitable nanoelectronic device for amplification purposes, low power analog and digital circuits, high-speed and low power applications

Investigation of a power FLIMOSFET based on two-dimensional numerical simulations

55-61This paper presents the numerical simulation results for a power FLIMOSFET structure with up to eleven vertical floating islands, designed using PISCES-IIB, a 2-dimensional advanced device simulator. The novel structure is based on the FLI-diode concept, which helps in lowering the maximum electrical field in the N–epitaxial region of the device to reduce the effective on–resistance without degrading device performance. Extensive simulations were performed to understand the device physics through various internal electrical quantities like potential distribution and electric field in different regions of the device both in on/off states. The effect of drift region doping on the device performance has been discussed. It is shown that the decrease in the drift region doping tends to decrease the electric field distribution and intermediate potential in this region thereby making its on-resistance lower than the value given by the conventional silicon limit. The device structure does not require any precise control of the boron implantation dose in the P+ floating islands for charge balance as essential in case of super junction (SJ)/COOLMOSTM devices. The process flow mechanism required to fabricate FLIMOSFET structure using multi-epitaxial technology has been discussed, which is less complex and less expansive than the super junction (SJ) devices technology